FPGA verification must address user uncertainty for prototyping, system validationSep 27th, 2011 | By admin | Category: Electronic Design, Technology
By Loring Wirbel
Senior Correspondent, Footwasher Media
The recent expansion and diversification of the FPGA verification market bears a certain resemblance to the ASIC verification market of 20 years ago, though beset with opposite challenges, thanks to the changes wrought in 20 years by Moore’s Law. When companies such as Quickturn Systems created large logic emulation systems to verify ASICs in the early 1990s, users had to be convinced to spend significant amounts of money while dedicated floor space equivalent to a mainframe, all to verify system ASICs. Today, FPGA verification can be addressed in add-in boards for a workstation, or even in embedded test points within the FPGA itself.
But even as customers in 1990 were reticent to move to logic emulation due to price tags, today’s FPGA verification customer may show some trepidation because such systems may seem simplistic, invisible, or of questionable value. In many cases, however, FPGA users dare not commit to multiple-FPGA systems (or to ASICs prototyped with FPGAs) without these tools. Newer generations of FPGAs, incorporating the equivalent of millions of gates, integrate RISC CPUs, DSP blocks, lookaside co-processors, and high-speed on-chip interconnect. Verification of such designs is a necessity, not a luxury.
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