Archive for February 2012

The roads less traveled around multicore walls

Feb 24th, 2012 | By

By Loring Wirbel and Lou Covey
A New Tech Press Report from Footwasher Media

For the better part of two decades, the processor industry has been running pell mell down the road of multicore design, packing more and more processor cores on a single chip.  But a funny thing happened on the way to the personal super computer.  It didn’t work.

In 2007, a DARPA study on the potential of an exascale computer concluded that with the current architecture of processors, in other words x86 and PowerPC, we could not get there from here.  As a result, in January 2012, …



ISQED Symposium

Feb 14th, 2012 | By

Title: ISQED Symposium
Location: Techmart Center, Santa Clara, California
Link out: Click here
Description: The International Symposium on Quality Electronic Design (ISQED)—the premier Electronic Design conference—bridges the gap between Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.
Start Date: 2012-03-19
Start Time: 09:00
End Date: 2012-03-21…



The future of multicore and 3D approaches at ISQED

Feb 7th, 2012 | By

As multicore processor design hits power, memory and ILP walls with increasing frequency, the established methodology is pinning much hope on 3D heterogenous approaches.  Those efforts will be described in detail in a series of best practices tutorials at this year’s ISQED symposium March 19, in the Techmart Center in Santa Clara, California.

Brian Leibowitz of Rambus Inc. will review the key specifications of memory subsystems and evaluate the advantages and limitations of a variety of design techniques such as low swing signaling, resonant clocking, DVFS, and fast power state transitions, as well as those of emerging 3D packaging methods.…