The future of multicore and 3D approaches at ISQED

Feb 7th, 2012 | By | Category: Electronic Design

As multicore processor design hits power, memory and ILP walls with increasing frequency, the established methodology is pinning much hope on 3D heterogenous approaches.  Those efforts will be described in detail in a series of best practices tutorials at this year’s ISQED symposium March 19, in the Techmart Center in Santa Clara, California.

Brian Leibowitz of Rambus Inc. will review the key specifications of memory subsystems and evaluate the advantages and limitations of a variety of design techniques such as low swing signaling, resonant clocking, DVFS, and fast power state transitions, as well as those of emerging 3D packaging methods.

Puneet Gupta, University of California, Los Angeles will address scaling of physical dimensions faster than the optical wavelengths or equipment tolerances used in the manufacturing line leading to increased process variability and low yields which make design process expensive and unpredictable. “Equivalent scaling” improvements – perhaps as much as one full technology generation, can come from looking “up” to circuit design.

As the semiconductor industry migrates toward extreme monolithic foundry level 3D heterogeneous structures for mixed-signal components and systems, Farhang Yazdani, president of BroadPak Corporation, will argue that 3D silicon/glass interposer and through silicon via (TSV) technology will play a significant role in next generation 3D packaging solutions.

Rafael Rios senior researcher in the Manufacturing Group at Intel, will explore the innovations that lead to extending Moore’s law into nano-scale feature sizes, including advances in device design, computational lithography, and materials engineering. We will also explore current research work looking into extending Moore’s law into the future.  Hsien-Hsin S. Lee, Georgia Institute of Technology will focus on  die-stacked 3D integration as the frontrunner technology to continue Gordon Moore’s prophecy in the vertical dimension. Stephen Pateras, product marketing director for Mentor Graphics Silicon Test Solutions group, will contend that 3D IC offers a compelling alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package.

Article sponsored by Element14.com

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